SystemVerilog Source Code Formatter

The SystemVerilog Formatter tool reorganizes SystemVerilog source text files to neatly indent code blocks according to their nesting level. It is a member of SD's family of Source Code Formatters.

SystemVerilog Formatter Features

• Formatted code compiles and synthesizes exactly like unformatted code
• Handles full SystemVerilog v3.1a
• Specification of indentation step distance
• Specification of arbitrary input tab column positions
• A version with obfuscation capability can make it difficult to understand by renaming variables

Semantic Designs also offers:

• SystemC Formatter
• Verilog Formatter
• VHDL Formatter

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