VHDL Source Code Formatter

The VHDLFormatter tool reorganizes VHDL source text files to neatly indent code blocks according to their nesting level. It is a member of SD's family of Source Code Formatters. An example of the VHDL Formatter's results can be seen here.

VHDL Formatter Features

  • Formatted code compiles and synthesizes exactly like unformatted code
  • Specification of indentation step distance
  • Specification of arbitrary input tab column positions
  • A version with obfuscation capability can make it difficult to understand by renaming variables and removing all formatting.

Semantic Designs also offers:

Download an evaluation copy

For more information: info@semanticdesigns.com    Follow us at Twitter: @SemanticDesigns