SystemVerilog Source Code Obfuscator

The SystemVerilog Obfuscator tool scrambles SystemVerilog source code to make it very difficult to understand or reverse-engineer . This provides significant protection for source code intellectual property that must be shipped to a customer. It is a member of SD's family of Source Code Obfuscators.

SystemVerilog Obfuscator Features

  • Handles full SystemVerilog 3.1a
  • Replaces names by nonsense names without affecting functionality
    • User definable list of preserved names
  • Strips comments and removes most source code structure
    • User definable comment filtering, to preserve Copyright and Synthesis directives
  • No changes to the customer SystemVerilog compilation or execution procedures or environment
  • Option to neatly format SystemVerilog source code as aid to developer before obfuscation
  • Output encoding in ASCII, European ASCII, or UNICODE
  • Command line and GUI interfaces

Download an evaluation version

Semantic Designs also offers a SystemC obfuscator, Verilog obfuscator, and a VHDL obfuscator.

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SystemVerilog
Obfuscator