Verilog Source Code Obfuscator

The Verilog Obfuscator tool scrambles Verilog source code to make it very difficult to understand or reverse-engineer (example). This provides significant protection for source code intellectual property that must be shipped to a customer. It is a member of SD's family of Source Code Obfuscators.

Verilog Obfuscator Features

• Handles full Verilog 1995 and 2001
• Replaces names by nonsense names without affecting functionality
  • User definable list of preserved names
• Strips comments and removes most source code structure
  • User definable comment filtering, to preserve Copyright and Synthesis directives
• No changes to the customer Verilog compilation or execution procedures or environment
• Option to neatly format Verilog source code as aid to developer before obfuscation
• Output encoding in ASCII, European ASCII, or UNICODE
• Command line and GUI interfaces
• Supports Xilinx tools requirements for uppercase symbols

Semantic Designs also offers a VHDL obfuscator, a SystemVerilog obfuscator, and a SystemC obfuscator.

Copyright © 1995-2008 Semantic Designs, Incorporated
DMS and "Design Maintenance System" are registered trademarks of Semantic Designs, Inc.
The SD logo and "Semantic Designs" are registered service marks of Semantic Designs, Inc.
CloneDR, PARLANSE and Thicket are trademarks of Semantic Designs, Inc.
The OMG logo is a registered trademark of the Object Management Group, Inc. in the United States and other countries.
To view our Privacy Policy, click here

Comments or problems: webmaster@semdesigns.com